for various energy levels of protection with minimal power consumption and write time penalties.
Our model is based on a classic 6 transistor inner core SRAM cell and an outer core consisting
of enhanced tri-state inverters. The outer core will absorb a particle strike at a sensitive node
of the SRAM cell without a major impact on write time performance or area overhead.
The model provides an on-demand protection due to the fact that the outer core
can be shut off during non-essential operating mode. The on-demand aspect of the design provides a
much more favorable power consumption overhead compared to the existing hardening technique.
The gains in power consumption overhead reduction increase as we scale down the process technology from 90nm
to 32nm. We simulated extensively our model and provided results for various energy levels of
soft error protection. We also compared our method to the standard hardening technique in terms of layout area,
performance and power consumption overhead for for 90nm, 65nm, 45nm and 32nm process technologies.
Regular Memory Cell SRAM with Tri-State Inverters SRAM Protected
Simulation Results
We demonstrated how the design of our SRAMT cell provides advantages in terms of performance and power consumption overhead
compared to the existing soft error protection techniques through transistor hardening.
Through simulations we were able to demonstrate that our new design provides identical energy levels of protection
to the existing protection techniques at minimal area overhead, while providing advantages in write time delay performance
and great reduction in power consumption for both average power and peak power during write time operation.
Our solution is also technology scalable, which is especially crucial for submicron designs.
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