----------------------------------------------------------------------- Problem 4.4 We could substitute into formula bottom page 213 (in text) (x31 x - 2^31) + (x30 x 2^30) + (x29 x 2^29) +...+ (x1 x 2^1) + (x0 x 2^0), to get answer. Because this two's complement number has predominantly digits, the formula will have many nonzero terms to add. The negation of this number will have mostly 0 digits, so using negation shortcut in the Example page 216 and remembering original sign will save enough work in the formula to be a good strategy. Thus, Negating 1111 1111 1111 1111 1111 1110 0000 1100 - base 2 is 0000 0000 0000 0000 0000 0001 1111 0011 + 1 = 0000 0000 0000 0000 0000 0001 1111 0100 Then the nonzero terms formula 2^8 + 2^7 + 2^6 + 2^5 + 2^ + 4 + 2^2 = 500 and the original sign is 1 meaning negative, so 1111 1111 1111 1111 1111 1110 0000 1100 - base 2 ------------------------------------------------------------------------- Problem 4.14 a) The sign bit is negative number. We first take its two's complement. A = 1000 1111 1110 1111 1100 0000 0000 0000 -A = 0111 0000 0001 0000 0100 0000 0000 0000 = 2^30 + 2^29 + 2^28 + 2^20 + 2^14 = 1,073,741,824 + 536,870,912 + 268,435,456 + 1,048,576 + 16,384 = 1,880,113,152 A = -1,880,113,152 b) A = 1000 1111 1110 1111 1100 0000 0000 0000 = 8FEFC000 = 2,414,854,144 c) s = 1 exp = 0001 1111 = 2^5 - 1 = 31 significant = 110 1111 1100 0000 0000 0000 (-1)^S x (1+signfic)x2^(exp-127) = -1x1.1101 1111 1x2^(-96) = -1 x(1+13 x 16^(-1) + 15 x 16^(-2) + 2^(-9)) x 2^(-96) = -1.873 x 2^(-96) = -2.364 x 10^(-29) d) opcode (6 bits) 100011 = lw rs (5 bits) = 11111 = 31 rt (5 bits) = 01111 = 15 address (16 bits) = 1100 0000 0000 0000 Since the address is negative we have to take two's complement. 2's complement is = 0100 0000 0000 0000 address = -2^14 = -16384 Therefore the instruction is lw 15, -16384(31) Notice address embedded within 16-bit immediate field is a byte address unlike constants embedded PC-relative branch instructions where word addressing is used. ---------------------------------------------------------------------- Problem 4.25 10 base 10 = 1010 base 2 = 1.01 x 2^3 Sign = 0 Significand = .01 Single exponent = 3 + 127 = 130 Double exponent = 3 + 1023 = 1026 Single precision 0 10000010 01000000000000000000000 Double precision 0 10000000010 0100000000000000000000000000000000000000000000000000 -------------------------------------------------------------------- Problem 4.28 -2/3= -1.01 * 2^(-1) Single exponent = -1 + 127 = 126 Double exponent = -1 + 1023 = 1022 Single precision 1 01111110 01010101010101010101010 trunc 01010101010101010101011 round Double precision 1 01111111110 0101010101010101010101010101010101010101010101010101 trunc 0101010101010101010101010101010101010101010101010110 round ---------------------------------------------------------------------------- Problem 4.29 main() { float x; printf("> "); scanf("%f", &x); printf("%08lx\n", * (long *) &x); } -------------------------------------------------------------------------- Problem 4.31 The IEEE number loaded easily into a register, $t0, as a word since it occupies 4 bytes. To multiply it by 2, recall that it is made up of three fields: a sign, exponent, and a fraction. The actual stored number is the fraction (with an implied 1) multiplied by a power of two. Hence to multiply the whole number by 2, simply add 1 to the the exponent! Note the following variations are incorrect: - Multiply the register $t0 by 2 (directly or thru sll) this is wrong because $t0 does not store integer. - Multiply fractional part by 2. This is correct in principle but the resulting number would need to be renormalized into IEEE format because the multiplication would shift the binary point. This would lead adding 1 to the expo nent! - Shift exponent left --this is wrong because amounts to squaring number rather than doubling it. To add 1 to the exponent (which occupies positions 23 through 30) in $t0, there are two ways (both ignore possible overflow): 1. Add $t0 to a $a0 where $a0 contains a number having zero bits everywhere except position 23. If a carry were to occur, this addition will change the sign bit, but we're ignoring floating-point overflow anyway. Here's the sequence: lw $t0, X($0) addi $a0, $0, 1 sll $a0, $a0, 23 addu $t0, $t0, $a0 sw $t0, X($0) 2. Isolate the exponent (possibly shifting left once then shifting 24 times to the right), add 1 to it, then shift it left 23 places to its proper place. To insert it back in its place, we start ``cleaning old exponent (by ANDing with appropriate mask) and then we OR cleaned $t0 with the incremented exponent. This method, albeit lengthy, is 100% acceptable. Here is a possible sequence: lw $t0, X($0) andi $t1, $t0, 0x7f800000 srl $t1, $t1, 23 addi $t1, $t1, 1 sll $t1, $t1, 23 and $t0, $t0, 0x807fffff or $t0, $t0, $t1 sw $t0, X($0) ----------------------------------------------------------------------------- Problem 4.40 xor $s0, $s0, $s1 xor $s1, $s0, $s1 xor $s0, $s0, $s1 ---------------------------------------------------------------------------- Problem 4.44 C1 = c4, C2 = c8, C3 = c12, C4 = c16 c8 in text c12 = G(11,8) + P(11,8)*G(7,4) + P(11,8)*P(7,4)*G(3,0) + P(11,8)*P(7,4)*P(3,0)*c0 c16 = G(15,12) + P(15,12)*G(11,8) + P(15,12)*P(11,8)*G(7,4) + P(15,12)*P(1,8)*P(7,4)*G(3,0) + P(15,12)*P(11,8)*P(7,4)*P(3,0)*c0 ---------------------------------------------------------------------------- Problem 4.49 Let A, B, E, F be four 4-bit nubers. The first Adder cirrcuit in Fig. 4.56 has 3 traditional adders 4-bit adders: Add1, Add2, and Add3. Add1 operates on nubers A and B as shown. The sum bits of A+B are fed into the left-port inputs of Add2. The right-port inputs of Add2 take the (bits of) number E. Similarly, the sum bits of (A+B)+E are fed into the left-port inputs of Add3. The right-port inputs of Add3 take the (bits of) number F. Finally, the sum bits of ((A+B)+E)+F = A+B+E+F are the outputs. The second adder circuit is the carry-save adder discussed in class. Here is again how it works. Let: A = 1 0 1 0 B = 1 1 0 0 E = 0 1 0 1 F = 0 0 1 1 Then First Row of additions are: 1 0 1 0 A 1 1 0 0 B 0 1 0 1 E --------- 0 0 1 1 3-way sum of A+B+E. Sums fed straight into the next stage. | | | | 1 1 0 0 3-way Carries of A+B+C. However, Carries are fed into next stage shifted Left. / / / / 0 0 1 1 3-way sum of A+B+E (from stage 1). 1 1 0 0 3-way Carries of A+B+C (from stage 1 shifted left). 0 0 1 1 F ----------------- 1 1 0 0 0 3-way 2nd stage Sum | | | | | 0 0 0 1 1 3-way 2nd stage Carries, to be shifted left for next stage. / / / / / / 1 1 0 0 0 Regular or Traditional 4-bit adder. 0 0 0 1 1 -------------- 0 1 1 1 1 0 Final Result of A+B+E+F _________________________________________________________________________ Problem 4.50 The longest paths through the top (ripple carry) adder circuit in Fig. 4.56 all start at input a0 or b0 and pass through seven full adders on the way to output s4 or s5. There are many such paths, all of having a time delay of 7 x 2T = 14T. The longest paths through the bottom (carry save) adder all start at input b0, e0, f0, b1, or f1 and proceed through six full adders to outputs s4 or s5. The time delay for this circuit is only 6 x 2T = 12T. ----------------------------------------------------------------------------