Please read the following paper (Week #15 link) ----------------------------------------------- http://bear.ces.cwru.edu/eecs_314/intel_pentium4_2001.pdf This is one of the most important papers to read as it will put all your class knowledge to work and understand Intel's latest technology :-) In order to help you read the paper, please be able to answer the following questions, as some of these will be asked on the exam: (1) What does the Trace Cache do? (2) Can the Trace Cache hold instructions and data? (3) What is out of order execution? (4) What are the tradeoffs in using higher clock rates? (5) What write-policy does the L1 cache? Associativity? Cache size? Cache-line size? and latency? (6) What write-policy does the L2 cache? Associativity? Cache size? Cache-line size? and latency? (6) What are stream-orientated applications? (7) What is the hardware prefetcher? Questions related to the Thursday handout: (1) If you write a 1 megabyte program, how big should cache size be, using the common sense rule of thumb? (2) If you have a 1 GHZ processor at 1 CPI, which "always hits" the cache, what are the MIPS? (3) If you have a 1 GHz processor at 1 CPI which "always misses" the cache, (assume 1000ns main memory access), what are the MIPS? (4) What are the MIPS for 25% miss? --Prof. Wolff.