-- -- VHDL Ripple Adder Test Bench, Wakerly Figure 5-87, page 432 -- -- EECS 281: http://bear.ces.cwru.edu/eecs_281/addfulltb.vhd -- Date: April 3, 2005 -- LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY AddFullTB IS END AddFullTB; -- Read about "Test benches" in Wakerly Table 4-65, page 296. -- ARCHITECTURE AddFullTB_arch OF AddFullTB IS COMPONENT AddFull PORT( x, y, Cin: IN std_logic; s, Cout: OUT std_logic ); END COMPONENT; SIGNAL x0, y0, c0, s0: std_logic; --WIRES SIGNAL x1, y1, c1, s1: std_logic; SIGNAL c2: std_logic; BEGIN --READ Ripple adders in Wakerly Figure 5-87 on page 432 --NOTICE the Cout of U0 is connected to the Cin of U1 U0: AddFull PORT MAP (x0, y0, c0, s0, c1); --adder #1 U1: AddFull PORT MAP (x1, y1, c1, s1, c2); --adder #2 PROCESS BEGIN -- Read about "Waveforms" in Wakerly section 4.7.9, page 295. x0 <= '0'; y0 <= '0'; c0 <= '0'; WAIT FOR 5 ns; assert ( s0 = '0' ) report "Failed Sum!=0 FOR x=0 y=0 Cin=0" severity error; assert ( c1 = '0' ) report "Failed Cout!=0 FOR x=0 y=0 Cin=0" severity error; WAIT FOR 5 ns; x0 <= '1'; y0 <= '1'; c0 <= '0'; wait for 5 ns; assert ( s0 = '0' ) report "Failed Sum!=0 FOR x=1 y=1 Cin=0" severity error; assert ( c1 = '0' ) report "Failed Cout!=1 FOR x=1 y=0 Cin=1" severity error; WAIT FOR 5 ns; WAIT; END PROCESS; END AddFullTB_arch;