--
-- VHDL full adder, Wakerly Figure 5-86, page 431
--
-- EECS 281: http://bear.ces.cwru.edu/eecs_281
-- Date: April 3, 2005
--

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Read about "Entity" in Wakerly Table 4-27 page 270.
--
ENTITY AddFull IS
  PORT( x, y, Cin    : IN  std_logic;
        s, Cout      : OUT std_logic );
END AddFull;

-- Read about "Architecture" in Wakerly Table 4-28 page 271.
--
ARCHITECTURE AddFull_arch OF AddFull IS
BEGIN
  -- Read about "full adders" in Wakerly Figure 5-86, page 431
  s    <= x XOR y XOR Cin;

  Cout <= (x AND y) OR (x AND Cin) OR (y AND Cin);
END AddFull_arch;