EC2: VHDL Extra Credit #2
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(30 points, Due: April 21)

(A) Work though the VHDL Simili QUICK TUTORIAL given below. Of course,
    learn to use the Help menu and Google to search the web for additional questions.

(B) Hand-in "paper" screen shots of simulator
    after adding several numbers (1111+0001; 1010+0101; and 0111+0011),
    study on your own from the Wakerly pages given in the "addfull.vhd"
    and "addfulltb.vhd" and explain the vhdl source code.

(C) Make sure your signals give the CORRECT results. Do not just
    run the simulator and hand-in the screen-shot.

(D) Also, hand-in "paper" and floppy/cdrom copies of your source file: add4tb.vhd

INSTALLATION
1. Create a directory on your computer called eecs_281

1a. Using Windows Explorer:  
1b. Start => All Programs => Accessories => Windows Explorer

    1a. OR using MsDos: 
    1b. MsDos Command Prompt: cd c:\
    1c. MsDos Command Prompt: mkdir eecs_281

2. Within VHDL, create another directory called ADD1
    2a. MsDos Command Prompt: cd c:\eecs_281
    2b. MsDos Command Prompt: mkdir ADD1

3. Download addfull.vhd and addfulltb.vhd into the
   ADD1 directory using the "Save Link As" on your
   web browser from 
     http://bear.ces.cwru.edu/addfull.vhd 
     http://bear.ces.cwru.edu/addfulltb.vhd 

4. Download and install the simulator at http://www.symphonyeda.com/

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VHDL Simili QUICK TUTORIAL
  FIRST TIME
   (a) File => New Workspace =>  Workspace name: ADD1 and Workspace location: c:\eecs_281\ADD1
   (b) Project => Add Files: addfull.vhd, addfulltb.vhd
   OTHER TIMES
   (a) File => Open Workspace
 
   COMPILE
   (a) Compile => Compile All
       Read the window label "Console" and check for any errors.
   SIMULATE
   (a) Simulate => Select Toplevel... => addfulltb(addfulltb_arch)
   (b) Simulate => Restart
   (c) Click on "Hierarchy" tab and Click on "addfulltb" within Workspace window
   (d) Move mouse in "Scope=:addfulltb:" window. Click on the signal "x0". Click-and-hold
       the right mouse button and scroll down to "Add to selected waveform".
       Do this for y1, c0, s0, c1. The signals should appear in the waveform viewer.
   (e) Simulate => Run
       This will simulate the test bench for 100ns.
       The "hand-lense +" will allow you to zoom in on the signal.
   (f) LOOK at the Console Window:
       ASSERT: ERROR at 15 ns+0: Failed Cout!=1 FOR x=1 y=0 Cin=1
          At addfulltb.vhd: (line 43)
           Instance = :addfulltb(addfulltb_arch):
           Simulation stopped at: 100 ns
           Elapsed Time: 00h:00m:00s:010ms

       *** There is an error in the testbench! ***
       The error could be in the "AddFull" or in the "AddFullTB". 

       Looking at the "AddFullTB" code in Line 43:
          assert ( c1 = '0' ) report "Failed Cout!=1 FOR x=1 y=0 Cin=1" severity error;
       should be
          assert ( c1 = '1' ) report "Failed Cout!=1 FOR x=1 y=0 Cin=1" severity error;

       We need to end the simulation and go to the editor.

   (f) Simulate => End Simulation
       This will end the simulation and allow to go back to edit mode.

   EDIT
   (a) Click on the "Files" tab. Double-Click on "addfulltb.vhd". 
***(b) Fix the test case in Line 43 to
          assert ( c1 = '1' ) report "Failed Cout!=1 FOR x=1 y=0 Cin=1" severity error;

   (c) File => Save
   (d) Goto COMPILE step and then SIMULATE step to check design.
   
   EXIT
   (a) File => Close Workspace
   (b) File => Exit (and Yes to save waveform file)