Synopsys 1076 VHDL Simulator Version 2000.12 -- Dec 26, 2000

	        Copyright (c) 1990-2000 by Synopsys, Inc.
	                    ALL RIGHTS RESERVED
	This program is proprietary and confidential information
	of  Synopsys, Inc. and may be used and disclosed only as
	authorized in a  license agreement  controlling such use
	and disclosure.


--begin test;
hello, world: stdlib_h_test
strtoul base=10 123=123 endptr= 4=4
strtoul base=8   64=83 endptr= 4=4
strtoul base=16 291=291 endptr= 4=4
strtoul base=16 291=291 endptr= 4=4
strtoul base=0  123=123 endptr= 4=4
strtoul base=0   83=83 endptr= 5=5
strtoul base=0  291=291 endptr= 6=6
strtoul base=0  291=291 endptr= 6=6
atoi    base=10 123=123
atoi    base=10 -123=-123
atoi    base=10 +123=123
--end test;
(vhdlsim): Simulation complete, time is 0 NS.