Symphony EDA (R) VHDL Compiler/Simulator Module VhdlP, Version 2.3, Build#8. Copyright(C) Symphony EDA 1997-2004. All rights reserved. Reading C:\Program Files\Symphony EDA\VHDL Simili 2.3\bin\symphony.ini ... Library 'ieee' ==> $SYMPHONYEDA/lib/ieee/ieee.sym (readonly) Library 'c' ==> c.sym Library 'work' ==> Library 'c' ==> c.sym Reading $SYMPHONYEDA\lib\ieee\ieee.sym\std_logic_1164\prim.var Parsing Package:ctype_h @ line ..\..\ctype_h.vhd:28 Writing c.sym\ctype_h\prim.var Parsing Package Body:ctype_h @ line ..\..\ctype_h.vhd:69 Writing c.sym\ctype_h\_body.var Elapsed Time: 00h:00m:00s:050ms Kernel Time: 00h:00m:00s:150ms User Time: 00h:00m:00s:090ms Symphony EDA (R) VHDL Compiler/Simulator Module VhdlP, Version 2.3, Build#8. Copyright(C) Symphony EDA 1997-2004. All rights reserved. Reading C:\Program Files\Symphony EDA\VHDL Simili 2.3\bin\symphony.ini ... Library 'ieee' ==> $SYMPHONYEDA/lib/ieee/ieee.sym (readonly) Library 'c' ==> c.sym Library 'work' ==> Library 'c' ==> c.sym Parsing Package:strings_h @ line ..\..\strings_h.vhd:35 Writing c.sym\strings_h\prim.var Parsing Package Body:strings_h @ line ..\..\strings_h.vhd:65 Writing c.sym\strings_h\_body.var Elapsed Time: 00h:00m:00s:040ms Kernel Time: 00h:00m:00s:130ms User Time: 00h:00m:00s:070ms Symphony EDA (R) VHDL Compiler/Simulator Module VhdlP, Version 2.3, Build#8. Copyright(C) Symphony EDA 1997-2004. All rights reserved. Reading C:\Program Files\Symphony EDA\VHDL Simili 2.3\bin\symphony.ini ... Library 'ieee' ==> $SYMPHONYEDA/lib/ieee/ieee.sym (readonly) Library 'c' ==> c.sym Library 'work' ==> Library 'c' ==> c.sym Parsing Package:debugio_h @ line ..\..\debugio_h.vhd:26 Writing c.sym\debugio_h\prim.var Parsing Package Body:debugio_h @ line ..\..\debugio_h.vhd:39 Writing c.sym\debugio_h\_body.var Elapsed Time: 00h:00m:00s:120ms Kernel Time: 00h:00m:00s:120ms User Time: 00h:00m:00s:090ms Symphony EDA (R) VHDL Compiler/Simulator Module VhdlP, Version 2.3, Build#8. Copyright(C) Symphony EDA 1997-2004. All rights reserved. Reading C:\Program Files\Symphony EDA\VHDL Simili 2.3\bin\symphony.ini ... Library 'ieee' ==> $SYMPHONYEDA/lib/ieee/ieee.sym (readonly) Library 'c' ==> c.sym Library 'work' ==> Library 'c' ==> c.sym Reading c.sym\ctype_h\prim.var Reading $SYMPHONYEDA\lib\ieee\ieee.sym\std_logic_1164\prim.var Parsing Package:stdlib_h @ line ..\..\stdlib_h.vhd:25 Writing c.sym\stdlib_h\prim.var Parsing Package Body:stdlib_h @ line ..\..\stdlib_h.vhd:48 Writing c.sym\stdlib_h\_body.var Elapsed Time: 00h:00m:00s:040ms Kernel Time: 00h:00m:00s:140ms User Time: 00h:00m:00s:060ms Symphony EDA (R) VHDL Compiler/Simulator Module VhdlP, Version 2.3, Build#8. Copyright(C) Symphony EDA 1997-2004. All rights reserved. Reading C:\Program Files\Symphony EDA\VHDL Simili 2.3\bin\symphony.ini ... Library 'ieee' ==> $SYMPHONYEDA/lib/ieee/ieee.sym (readonly) Library 'c' ==> c.sym Library 'work' ==> Library 'c' ==> c.sym Reading c.sym\strings_h\prim.var Parsing Package:regexp_h @ line ..\..\regexp_h.vhd:27 Writing c.sym\regexp_h\prim.var Parsing Package Body:regexp_h @ line ..\..\regexp_h.vhd:67 Writing c.sym\regexp_h\_body.var Elapsed Time: 00h:00m:00s:070ms Kernel Time: 00h:00m:00s:140ms User Time: 00h:00m:00s:090ms Symphony EDA (R) VHDL Compiler/Simulator Module VhdlP, Version 2.3, Build#8. Copyright(C) Symphony EDA 1997-2004. All rights reserved. Reading C:\Program Files\Symphony EDA\VHDL Simili 2.3\bin\symphony.ini ... Library 'ieee' ==> $SYMPHONYEDA/lib/ieee/ieee.sym (readonly) Library 'c' ==> c.sym Library 'work' ==> Library 'c' ==> c.sym Reading $SYMPHONYEDA\lib\ieee\ieee.sym\std_logic_1164\prim.var Reading c.sym\strings_h\prim.var Reading c.sym\regexp_h\prim.var Reading c.sym\stdlib_h\prim.var Reading c.sym\ctype_h\prim.var Parsing Package:stdio_h @ line ..\..\stdio_h.vhd:31 Writing c.sym\stdio_h\prim.var Parsing Package Body:stdio_h @ line ..\..\stdio_h.vhd:260 Writing c.sym\stdio_h\_body.var Elapsed Time: 00h:00m:00s:250ms Kernel Time: 00h:00m:00s:150ms User Time: 00h:00m:00s:190ms Symphony EDA (R) VHDL Compiler/Simulator Module VhdlP, Version 2.3, Build#8. Copyright(C) Symphony EDA 1997-2004. All rights reserved. Reading C:\Program Files\Symphony EDA\VHDL Simili 2.3\bin\symphony.ini ... Library 'ieee' ==> $SYMPHONYEDA/lib/ieee/ieee.sym (readonly) Library 'work' ==> work.sym Reading $SYMPHONYEDA\lib\ieee\ieee.sym\std_logic_1164\prim.var Library 'c' ==> c.sym Reading c.sym\stdio_h\prim.var Reading c.sym\stdlib_h\prim.var Reading c.sym\ctype_h\prim.var Reading c.sym\regexp_h\prim.var Reading c.sym\strings_h\prim.var Parsing Entity:stdio_h_test @ line stdio_h_test.vhd:29 Writing work.sym\stdio_h_test\prim.var Parsing Architecture:stdio_h_test(stdio_h_test_arch) @ line stdio_h_test.vhd:32 Writing work.sym\stdio_h_test\_stdio_h_test_arch.var Parsing Configuration:stdio_h_test_cfg @ line stdio_h_test.vhd:467 Writing work.sym\stdio_h_test_cfg\prim.var Elapsed Time: 00h:00m:00s:110ms Kernel Time: 00h:00m:00s:090ms User Time: 00h:00m:00s:160ms Symphony EDA (R) VHDL Compiler/Simulator Module VhdlE, Version 2.3, Build#8. Copyright(C) Symphony EDA 1997-2004. All rights reserved. Note: CSVHE0051: vhdle: Thank you for using the free version of from VHDL Simili. Warning: CSVHE0055: vhdle: Simulator will run at reduced perfomance and with certian features disabled Reading C:\Program Files\Symphony EDA\VHDL Simili 2.3\bin\symphony.ini ... Library 'ieee' ==> $SYMPHONYEDA/lib/ieee/ieee.sym (readonly) Library 'work' ==> work.sym Reading work.sym\stdio_h_test_cfg\prim.var Reading work.sym\stdio_h_test\_stdio_h_test_arch.var Library 'c' ==> c.sym Reading c.sym\strings_h\_body.var Reading c.sym\stdio_h\_body.var Reading c.sym\stdlib_h\_body.var Reading c.sym\ctype_h\_body.var Reading $SYMPHONYEDA\lib\ieee\ieee.sym\std_logic_1164\_body.var Reading c.sym\regexp_h\_body.var Warning: ****Reducing simulation speed to super slow mode! # of Signals = 0 # of Components = 0 # of Processes = 1 # of Drivers = 0 Design Load/Elaboration Elapsed Time: 00h:00m:00s:120ms --begin test; Time: 0 ps+0 abc def x07 signed decimal %d=-2 == -2 x16 unsigned hex %x=e == e z16 unsigned hex %x=0 == 0 b07(7)=1 b07(6)=0 b07(5)=1 b07(4)=0 b07(3)=1 b07(2)=1 b07(1)=0 b07(0)=0 b07 unsigned string %s=10101100 == 10101100 (print as big endian) b07 unsigned hex %x=ac == ac b07 unsigned octal %o=254 == 254 b07 unsigned decimal %u=172 == 172 b07 signed decimal %d=-84 == -84 b07 %5x=[ ac] == [ ac] b07 %05x=000ac == 000ac b07 %#x=0xac == 0xac b07 %X=AC == AC b07 %#X=[0XAC] == [0XAC] b07 %#1X=[0XAC] == [0XAC] b07 %#5X=[ 0XAC] == [ 0XAC] b07 %#9X=[ 0XAC] == [ 0XAC] b07 %-#9X=[0XAC ] == [0XAC ] b07 %-#09X=[0XAC ] == [0XAC ] b07 %#05X=[0X0AC] == [0X0AC] b07 %#09X=[0X00000AC] == [0X00000AC] b07 %-x=ac == ac b07 %+x=ac == ac b07 %1d=[-84] == [-84] b07 %5d=[ -84] == [ -84] b07 %9d=[ -84] == [ -84] b07 %-9d=[-84 ] == [-84 ] b07 %09d=[-00000084] == [-00000084] variable b70: bit_vector(7 downto 0):=11001010; --initialize as big endian b70(7)=1 b70(6)=1 b70(5)=0 b70(4)=0 b70(3)=1 b70(2)=0 b70(1)=1 b70(0)=0 b70 %#s=11001010 == 11001010 b70 %#x=0xca == 0xca b70 %#o=0312 == 0312 b70 %#d=-54 == -54 b07:=bit_vector'(00110101); == bit_vector'(b0,...,b6,b7) b07 =[10101100] == [10101100] == [b7,b6,...,b0] b70:=bit_vector'(11001010); == bit_vector'(b7,...,b1,b0) b70 =[11001010] == [11001010] == [b7,b6,...,b0] v07:=std_logic_vector'(0LWXU1Z-); == std_logic_vector'(v0,...,v6,v7) v07 =[-Z1UXWL0] == [-Z1UXWL0] == [v7,v6,...,v0] v70:=std_logic_vector'(-Z1UXWL0); == std_logic_vector'(v7,...,v1,v0) v70 =[-Z1UXWL0] == [-Z1UXWL0] == [v7,v6,...,v0] variable b07: bit_vector(0 to 7):=00110101; --initialize as little endian b70 := b07; --effects of mis-matched endian copy b70(7 DOWNTO 0):= b07(0 TO 7); --same as b70:=b07; b70(7)=0 b70(6)=0 b70(5)=1 b70(4)=1 b70(3)=0 b70(2)=1 b70(1)=0 b70(0)=1 b70 %s=00110101 b70 %x=35 std_logic_vector(15 downto 0)=12AF=0001001010101111 std_logic_vector(15 downto 0)=012A=0000000100101010 integer=27==27 %s=[hello,]=[hello,] scanf([ 12ab 456 ]==[ 12ab 456],...);; %d=12==12 %x=12ab==12ab %s=00001001010101011==00001001010101011 %o=12==12 scanf([ 01001100 456 ]==[ 01001100 456 ],...); bool %s=0==0 bool %x=0==0 bit %s=0==0 bit %x=0==0 scanf([ 11001100 456 ]==[ 11001100 456 ],...); bool %s=1==1 bool %x=1==1 bit %s=1==1 bit %x=1==1 b07 %s=11111100==11111100 b07 %x=fc==fc b70 %s=11111100==11111100 b70 %x=fc==fc scanf([ H10Xhlwu 456 ]==[ H10Xhlwu 456 ],...); std_logic %s=H==H sl1 %x=0==0 v07 %s=H10XHLWU==H10XHLWU v07 %x=40==40 v70 %s=H10XHLWU==H10XHLWU v70 %x=40==40 ----------------begin FILE I/O tests----------------- fopen(xxx_out.txt) fout=4 == 4 fopen(xxx_fout1.txt) fout1=4 == 4 fopen(xxx_fout2.txt) fout2=5 == 5 fopen(xxx_out.txt) fin=4 == 4 s=hel==hel fgetc(1..5)=[lo, ]==[lo, ] s=world==world s=123==123 s=9bc==9bc fopen(/dev/tty, r) fin=2 == 2 fopen(/dev/tty, w) fout=1 == 1 fopen(/dev/null) fout=3 == 3 fopen(CON, r) fin=2 == 2 fopen(CON, w) fout=1 == 1 fopen(NUL, r) fin=3 == 3 fopen(NUL, w) fout=3 == 3 fopen(stdio_inlet_test_file.txt) fin=4 ==4 vhdl external input: s=0xx10uhh vhdl external input: s=0123 vhdl external input: s=uuuu vhdl external input: s=-23 vhdl external input: s=0x123 fopen(unknown.txt) fin=0 == 0 ----------------end FILE I/O tests----------------- ----------------begin REAL FLOATING POINT tests----------------- real float f=3.141590e+00 == 3.141590e+00 real float 2.953000e+01 == 2.953000e+01 sscanf( 365.25 , %f, g); g=3.652500e+02 == 3.652500e+02 ----------------end REAL FLOATING POINT tests----------------- --string'(little endian), std_logic_vector'(little_endian), bit_vector'(little std_logic_vector'(H1001XL)=[LX1001H] == [LX1001H] std_logic=1 == 1 Note using pf(): pf(std_logic_vector)=[01001X0 ] == [01001X0 ] std_logic_vector=[01001X0 ]==[01001X0 ] std_logic=[1 ]==[1 ] %+ #-0.0s=[] == [] %0.0s =[] == [] %10s =[hello, world] == [hello, world] %10.0s =[ ] == [ ] %.10s =[hello, wor] == [hello, wor] %0.10s =[hello, wor] == [hello, wor] %-10s =[hello, world] == [hello, world] %-10.0s =[ ] == [ ] %.15s =[hello, world] == [hello, world] %0.15s =[hello, world] == [hello, world] %-15s =[hello, world ] == [hello, world ] %-15.0s =[ ] == [ ] %15.10s =[ hello, wor] == [ hello, wor] %-15.10s=[hello, wor ] == [hello, wor ] %-5.10s =[hello, wor ] == [hello, wor ] true =[1] == [1] false =[0] == [0] std_logic=[H] == [H] %s =[0] == [0] == 0 %s =[11] == [11] == -1 (minimum number of bits) %d =[-1] == [-1] == -1 %s =[1001] == [1001] == -7 %u =[9] == [9] == -7 (unsigned =9) %d =[-7] == [-7] == -7 %s =[10001] == [10001] == -15 %s =[01111] == [01111] == 15 %d =[15] == [15] == 15 %#3d =[1945] == [1945] % 3d =[ 1945] == [ 1945] % +3d =[+1945] == [+1945] %+ 3d =[+1945] == [+1945] %+3d =[+1945] == [+1945] %3d =[1945] == [1945] %3d =[-2047] == [-1945] %10x =[ 799] == [ 799] == 1945 %#10x =[ 0x799] == [ 0x799] == 1945 %#10o =[ 03631] == [ 03631] == 1945 %s =[011110011001] == [0011110011001] == 1945 (first bit is sign) %10x =[ 801] == [ 1867] == -1945 %10x =[ 0x801] == [ 0x1867] == -1945 %s =[100000000001] == [1100001100111] == -1945 (first bit is sign) %10d =[ 1945] == [ 1945] %10d =[ -2047] == [ -1945] %010d =[0000001945] == [0000001945] %010d =[-000002047] == [-000001945] % 010d =[0000001945] == [0000001945] % 010d =[-000002047] == [-000001945] %+010d =[+000001945] == [+000001945] %+010d =[-000002047] == [-000001945] --big endian x'799' is same as little endian bit_vector'(x'99e'); --big endian o'3631' is same as little endian bit_vector'(o'4636'); --use vhdl library endian_h to avoid these difficulties bit_vector %s =[011110011001] == [11110011001]==1945 bit_vector %s =[011110011001] == [11110011001]==1945 bit_vector %s =[011110011001] == [11110011001]==1945 bit_vector %12s =[011110011001] == [11110011001]==1945 bit_vector %d =[1945] == 1945 std_logic_vector %d =[1945] == [1945] std_logic_vector %10d =[ 1945] == [ 1945] std_logic_vector %u =[1945] == [1945] std_logic_vector %10u =[ 1945] == [ 1945] std_logic_vector %x =[799] == [799] std_logic_vector %#x =[799] == [799] std_logic_vector %10x =[ 799] == [ 799] std_logic_vector %o =[3631] == [3631] std_logic_vector %#o =[3631] == [3631] std_logic_vector %10o =[ 3631] == [ 3631] -------------Bug Fix for Version 22--------------- printf(%d = 3 == 3); printf(%s = 011 == 011); printf(%x = 3 == 3); printf(%s = 0100 == 0100); printf(%x = 4 == 4); printf(%s = 0101 == 0101); printf(%x = 5 == 5); printf(%s = 010011 == 010011); printf(%x = 13 == 13); scanf(12, %d,i); printf(%d = 12 == 12); scanf(12, %d,i); printf(%s = 01100 == 01100); scanf(12, %d,i); printf(%x = c == c); scanf(12, %x,i); printf(%d = 18 == 18); scanf(12, %x,i); printf(%s = 010010 == 010010); scanf(12, %x,i); printf(%x = 12 == 12); scanf(80, %x,i); printf(%s = 010000000 == 010000000); scanf(80, %x,i); printf(%x = 80 == 80); scanf(80, %x,i); printf(%d = 128 == 128); scanf(128,%d,i); printf(%x = 80 == 80); scanf(128,%d,i); printf(%d = 128 == 128); printf(%x = 7f == 7f, 127); printf(%x = 177 == 177, 127); printf(%d = 127 == 127, 127); v1=1001 v2=011001 v3=110011001 v4=10011001111 time is 5 ==5 ns time is now 0 ==0 ns -------------checking stdio_h internal functions--------------- --copy line to string strcpy(s, w.all); s=[Konnichi wa] w.all=[Konnichi wa] --copy string line w:=NEW string'(Bonjour); --copy string to line strcpy(w.all, s); w.all=[Konnich]==[Konnich] s=[Konnichi wa]==[Konnichi wa] write(w, string'(Konnichi )); write(w, string'(Wa)); --similar to strcat(w, Konnichi ); strcat(w, Wa); s=(Konnichi Wa) == (Konnichi Wa) --printf(s=(%s)n, *w); w'length=11==11 --strlen(*w); hello1 hello2 fi=17==17 sprintf=(hello3 hello4 )=(hello3nhello4n) strlen(w)=w'length=14==14 fi=17==17 sscanf matched=(123abch) == (123abch) sscanf unused =( 456 ) == ( 456 ) strlen(w)=7==7 fi=3==3 sscanf matched=(12) == (12) sscanf unused =(3abch 456 ) == (3abch 456 ) strlen(w)=2==2 fi=4==4 sscanf matched=(01111011) == (001111011) == 123 sscanf unused =(abch 456 ) == (abch 456 ) strlen(w)=8==9 fi=3==3 sscanf matched=(0000100100011101010111100) == (0000100100011101010111100) sscanf matched=(123abc) == (123abc) sscanf unused =(h 456 ) == (h 456 ) strlen(w)=25==25 fi=3==3 hello, world 123 9bc %xyz++abc ***%...def 555 --end test; Simulation stopped at: 0 ps Warning: CSSIM0017: Found 8 ACCESS type object(s) that were never deallocated Note: CSSIM0018: ../../stdio_h.vhd: (line 1068): 1 Leaked ACCESS object(s) allocated at this line Note: CSSIM0018: ../../stdio_h.vhd: (line 1124): 1 Leaked ACCESS object(s) allocated at this line Note: CSSIM0018: ../../stdio_h.vhd: (line 729): 1 Leaked ACCESS object(s) allocated at this line Note: CSSIM0018: ../../stdio_h.vhd: (line 665): 5 Leaked ACCESS object(s) allocated at this line Simulation Elapsed Time: 00h:00m:13s:229ms Total Kernel Time: 00h:00m:00s:320ms Total User Time: 00h:00m:12s:878ms